1. Field of the Invention
The present invention relates to a semiconductor memory device with clocked column redundancy and time-shared redundancy data transfer approach, particularly to an electrically-programmable non-volatile semiconductor memory device such as an EPROM, an EEPROM or a Flash EEPROM.
2. Discussion of the Related Art
It is known that semiconductor memory devices comprise a matrix of memory cells arranged in rows (word lines) and columns (bit lines).
It is also known to provide semiconductor memory devices with a so-called column redundancy circuit comprising redundancy bit lines of redundancy memory cells, useful for functionally replacing defective bit lines in the memory matrix detected during the in-factory, post-manufacturing testing of the memory devices.
The column redundancy circuit comprises redundancy memory registers for storing addresses of the defective bit lines (defective addresses) and for comparing the stored defective addresses with a current address supplied to the memory device, so that when coincidence between the current address and a defective address is detected, selection of the defective bit line is prevented and a redundancy bit line is instead selected.
The provision of a column redundancy circuit in a memory device can occupy a significant area in the memory device chip, and generally complicates the design of the device layout, since several signal lines are necessary to route the signals through the chip. This limits the benefits, in term of manufacturing yield, of the provision of the column redundancy circuit.
In view of the state of the art described, it is an object of the present invention to provide a semiconductor memory device with a novel column redundancy architecture suitable to reduce the number of signal lines which are provided in the memory device chip.